The invention relates to a justification decision circuit for a circuit arrangement for bit rate adjustment of two signals, the circuit arrangement comprising an elastic store in which the data of a first signal can be written in parallel in groups of n bits each (n.gtoreq.1) and which elastic store is followed by a selection matrix, in that the arrangement for bit rate adjustment comprises a write counter for controlling the writing operation and a read counter for controlling the reading operation, in that the justification decision circuit comprises a subtractor for forming the difference between the counts and in that the subtractor, a controller and the read counter form a control loop.
A justification decision circuit having the above characteristic features is known from DE-A 39 22 897, to which U.S. Pat. No. 5,132,970 corresponds. Such a circuit arrangement is necessary in information transmission technology, for example, for plesiochronous multiplexers which combine plesiochronous signals. Two binary signals are called plesiochronous when their bit rates are nominally identical but may in fact differ from the nominal value within a given tolerance. Before plesiochronous signals are combined by a plesiochronous multiplexer, they are all to be brought to the same bit rate which (with the so-called positive justification technique) is higher than the bit rates the individual plesiochronous signals have. This bit rate difference is equalized, for example, in that so-called stuff bits are inserted from time to obtain a signal having a higher bit rate. The signal having the higher bit rate is to be structured in frames so that such stuff bits can again be removed after demultiplexing. Frames especially considered in this context are the so-called Synchronous Transport Modules STM-N (cf. for this purpose CCITT Recommendations G707, G708, G709). Such a frame is partitioned into rows and each individual row is structured in bytes. These frames contain justification locations for variable stuff bits in addition to justification locations for so-called fixed stuff bits. The justification locations for fixed stuff bits are always to accommodate fixed stuff bits, whereas the locations for the variable stuff bits are occupied either with an information bit or a stuff bit according to the decision of the justification decision circuit.
In the prior-art circuit arrangement the input signal is converted by a serial-to-parallel converter into eight (n=8) parallel bits--thus in bytes--and written into an elastic store byte by byte. The following embodiments are restricted for simplicity to the case where n=8, because the expert will be able to translate the other embodiments to the case where n=8. Both the writing operations and the reading operations are controlled by counters (write or read counters), which are timed by byte clocks. It is the object of serial-to-parallel conversion to execute a maximum number of components of the overall arrangement in power saving CMOS technology.
The problem of inserting stuff bits at predetermined locations in a parallel bit stream of eight parallel bits, is solved in the prior-art circuit arrangement by means of a controllable selection matrix. The exact description of the selection matrix is to be found in, for example, DE-A 39 20 391, to which U.S. patent application Ser. No. 07/935,149 corresponds.
A further problem occurring in the prior-art circuit is that the variable stuff bits are situated in such a way that they are distributed as uniformly as possible over the signal having the higher bit rate. If this is not accomplished, a non-uniform distribution of the bits leads to low-frequency jitter during demultiplexing. This jitter can no longer be eliminated with simple means. A uniform distribution of the stuff bits is difficult inasmuch as the subtractor produces the phase time difference between write and read counters (this time difference is understood to be the period of time the read counter needs to get from the count of the write counter to its own actual count) with an accuracy of only byte clock periods and the uniform distribution of the stuff bits requires that this difference is known with an accuracy of one bit clock period. A time standard is in this context a byte clock period or a bit clock period respectively, of the signal having the higher bit rate. For brevity byte or bit-accurate phase differences will be referred to in this connection.
The problem of uniformly stuffing single bits is solved in the prior-art arrangement by means of a controller with an integrating behaviour, which is included in a control loop comprising the subtractor and the read counter. In this arrangement the low-pass behaviour of the control loop leads to a time-dependent interpolation of the byte-accurate phase difference. A compromise can be found between the quality of the interpolation which requires a long time constant and a favourable locking behaviour or dynamic behaviour of this control loop.